1. Field of the Invention
The invention relates generally to the process and configuration for packaging integrated circuits such as power MOSFETs and other types of integrated circuits, such as power IC. More particularly, this invention relates to a novel and improved method and configuration for simplifying and streamlining the MOSFET and IC device package processes as highly integrated module to achieve lower production cost, higher packaging throughput and packages with improved reliability.
2. Description of the Prior Art
Packaging technologies as currently available and the configurations commonly implemented to package the vertical semiconductor devices, e.g., the power MOSFET devices, still face a problem that a leadframe or ceramic substrate is commonly used. There is a thermal mismatch between the metal lines of the leadframe and the printed circuit board (PCB) supporting the electronic device and the leadframe. Due to the thermal mismatch, there is a higher failure rate of solder joints. Furthermore, the conventional mechanical structure has several drawbacks such as the unevenness of the die-lead frame system, the limited die size due to the lead frame limitation, and limitation of stress absorption during board level mounting. Current packaging technologies further has another limitation where there is an assembly acceptance difficulty that often causes higher assembly cost and makes it difficult to replace the conventional high volume packages, such as SO, TO and TSSOP package families to reduce the packaging costs. Such difficulty is caused by the fact that these packages cannot be completely packaged by either a lead frame type packaging technology or a regular surface mount assembly technology. These packages further introduce another difficulty in the board level during the pre-assembly and testing processes due to the operations which are conducted under a sightless condition of the solder joint area between package and PCB. The use of lead frame in these packaging technologies further limits the package to a single die configuration because of the fact that the leadframes do not provide flexibilities to be adaptable to the multiple-chip configuration either as a single module or as an assembly comprised of several modules.
In U.S. Pat. No. 6,133,634 Joshi discloses a semiconductor package as that shown in FIG. 1A. A silicon die 102 is attached to a carrier 106 that has a cavity substantially surrounding the die 102. The cavity dimensions are designed such that the cavity depth is substantially equal to the thickness of die 102 plus the thickness of die attach bond line 104. Direct connection of the active surface of the silicon die to the printed circuit board (PCB) that includes electrical terminals to contact an array of solder bumps distributed across the bottom surface of the die and ball grid array BGA 108 on the bottom edges of the carrier 106 surrounding the die 102. The carrier 106 is formed either as copper or ceramic carrier. Even that this package has the benefits of reducing the package resistance and offers much improved thermal performance, the package has higher production cost due to the requirement to specially manufacture the carrier 106 with specially shaped cavity. Furthermore, due to the geometric shape of the carrier 106, the package as disclosed by Joshi still lacks the flexibility to adapt to different packaging configurations including the multiple-chip module (MCM) configuration.
In another U.S. Pat. No. 6,391,687 entitled “Column Ball Grid Array Package”, Cabahug et al. disclose a semiconductor device that includes a flat leadframe that includes a die attach area on a surface of the leadframe. A die including solder bumps is placed thereon and the package further includes a plurality of columns surround at least a portion of the periphery of the die attach area. The die is positioned within the die attach area and the columns have a height substantially equal to the solder bumps and the die on the leadframe as that shown in FIGS. 1B and 1C.
Standing et al. disclose in another U.S. Pat. No. 6,624,522 a chip scale package (CSP) that has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
Granada et al. disclose in another U.S. Pat. No. 6,661,082 a chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.
Joshi discloses in another U.S. Pat. No. 6,469,384 a semiconductor device that includes a substrate and a die coupled to the substrate. The MOSFET die is coupled to the substrate such that the source and gate regions of the MOSFET die are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections. As shown in FIG. 1D, the substrate includes a base layer 20 and a top, metal layer 21. The base layer and the top metal layer are separated by an insulting layer 22 that may be an insulating epoxy to join the two layers. The base material may comprise a metallized pattern while the top metal layer preferably comprises another metallized pattern. The metal layer may also serve as a heat spreader. However, since the at least one or two layers of this multi-layered substrate is composed of metal, the problem of thermal expansion mismatches between the metal layer and the printed circuit board for supporting the package would still cause thermal stresses. The package is still limited by a reliability problem when operated under thermally challenging environment. Furthermore, the substrate is still manufactured with specially design processes for the purpose of forming the metal layers. The production costs are therefore increased due to the special manufacturing requirements of the package substrate as disclosed in this patented invention.
A stackable three-dimensional multi-chip module (MCM) is disclosed in U.S. Pat. No. 5,222,014. As shown in FIG. 1E, each level of chip carrier in this stackable three-dimensional MCM is interconnected to another level of chip carrier through reflowing of solder balls pre-bumped onto each carrier. Each level of chip carrier, except for the top carrier, has solder balls on both top and bottom surfaces of the substrate. Optional lids can be used to seal each device, and the lid height would serve as a natural positive stand-off between each level of carriers, giving rise to hour glass shaped solder joints which maximizes the fatigue life of the joints. The packaging configuration disclosed in this patent provides a method to form a three-dimensional stackable module to increase the packing density of the multiple chips. However, it only applies to semiconductor chips where electrical contacts are formed on the same surface.
In U.S. Pat. No. 5,715,144, Ameen et al. disclose another multiple layered multiple chip module configured with a pyramid structure. Multiple tape automatic bonding (ATAB) carriers are used to support chips thereon to stack upon each other in a pyramid configuration and attached to a substrate for reducing the required area on the substrate for mounting components to form a circuit board. However, the ATAB carriers are too thin to maintain its shape, stiffeners need to be used to increase the complexity and package size. Furthermore the disclosed packaging technique is only applicable to package semiconductor chips where all electrical contacts are on the same surface (planar device). Similarly, the stacked packages as disclosed by Akram et al. in U.S. Pat. No. 5,994,166 as shown in FIG. 1F has the same limitations since each individual chip only contacts on one surface of the die.
Therefore, the above patented disclosures do not provide a practical solution to overcome the limitations and difficulties as now encountered by a person of ordinary skill in the art of semiconductor device packaging design and manufactures. Therefore, a need still exists in the art to provide a new and improved configuration and methods to package a vertical semiconductor device such that the above discussed problems and difficulties can be resolved. Furthermore, none of above disclosures can be used for 3D packaging for vertical power MOSFET device and power IC module.